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right: pcb adjust drc settings to reflect jlcpcb capabilities

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This commit is contained in:
phiwan-dev 2026-03-24 00:50:20 +01:00
parent ccc881c265
commit df15e95183
2 changed files with 48 additions and 9 deletions
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42
board/board_right.kicad_pro
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@ -51,7 +51,13 @@
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
@ -119,9 +125,9 @@
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_copper_edge_clearance": 0.2,
"min_groove_width": 0.0,
"min_hole_clearance": 0.25,
"min_hole_clearance": 0.2,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
@ -132,7 +138,7 @@
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"min_via_diameter": 0.4,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
@ -180,7 +186,12 @@
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"track_widths": [
0.0,
0.1,
0.2,
0.4
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
@ -207,7 +218,24 @@
"spacing": 0.6
}
},
"via_dimensions": [],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.4,
"drill": 0.3
},
{
"diameter": 0.45,
"drill": 0.3
},
{
"diameter": 0.6,
"drill": 0.4
}
],
"zones_allow_external_fillets": false
},
"ipc2581": {
@ -237,7 +265,7 @@
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"clearance": 0.1,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,